42551-00【PDF 2/9 页】KIT EVAL FOR 42551 RF SWITCH

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PE42551

Product Specification

Figure 3. Pin Configuration (Top View)

Table 3. Absolute Maximum Ratings

Symbol

V DD

V I

V CTRL

V LS

T ST

T OP

Parameter/Conditions

Power supply voltage

Voltage on any input except

for CTRL and LS inputs

Voltage on CTRL input

Voltage on LS input

Storage temperature range

Operating temperature range

Min

-0.3

-0.3

-65

-40

Max

4.0

V DD +

0.3

4.0

4.0

150

85

Units

V

V

V

V

°C

°C

Input Power 50 ? :

P IN

V ESD

9 kHz ≤ 4 MHz

4 MHz ≤ 6 GHz

ESD voltage HBM 1

Fig. 4

31

500

dBm

dBm

V

Note: 1. Human Body Model (HBM, MIL_STD 883 Method 3015.7)

Table 2. Pin Descriptions

Exceeding absolute maximum ratings may cause

permanent damage. Operation should be

RF2 port.

Pin No.

13

Pin Name

RF2

1

Description

restricted to the limits in the Operating Ranges

table. Operation between operating range

maximum and absolute maximum for extended

1, 2, 4, 5,

Ground Connection. Traces should be

physically short and connected to the

periods may reduce reliability.

6, 7, 9, 10,

11, 12, 14,

15, 19

3

16

8

17

18

20

Paddle

GND

RF1

CTRL

RFC

LS

V SS

V DD

GND

ground plane. This pin is connected to

the exposed solder pad that also must

be soldered to the ground plane for best

performance.

RF1 port. 1

CMOS level (See Table 5 )

Common RF port for switch 1

Logic Select - Used to determine the

definition for the CTRL pin (see

Table 5 )

Negative power supply. Apply nominal

-2.75V supply 2

Nominal 2.75V supply connection

Exposed Ground Paddle

Electrostatic Discharge (ESD) Precautions

When handling this UltraCMOS ? device, observe

the same precautions that you would use with

other ESD-sensitive devices. Although this device

contains circuitry to protect it from damage due to

ESD, precautions should be taken to avoid

exceeding the rating specified.

Moisture Sensitivity Level

The Moisture Sensitivity Level rating for the

PE42551 in the 20-lead 4x4x0.85 mm QFN

package is MSL1.

Notes: 1. All RF pins must be held at 0 VDC or the DC must be blocked with

an external series capacitor

2. Use V SS (pin 13, V SS = -V DD ) to bypass and disable internal negative

voltage generator. Connect V SS (pin 13) to GND (V SS = 0V) to enable

internal negative voltage generator.

?2010-2012 Peregrine Semiconductor Corp. All rights reserved.

Latch-Up Avoidance

Unlike conventional CMOS devices, UltraCMOS ?

devices are immune to latch-up.

Document No. 70-0350-02 │ UltraCMOS ? RFIC Solutions

Page 2 of 9

Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com

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